As highly integrated LSI chips have been developed, strong demand has arisen for a decrease in package size, and thus a variety of packaging structures have been proposed. In recent years, attempts have been made to develop a process for forming through-electrodes in semiconductor bare chips, and stacking the semiconductor bare chips. Meanwhile, there is a high likelihood of commercialization of a real-size packaged device having electrodes on its both surfaces. As a variety of multifunctional, small electronic apparatuses have been developed, a semiconductor device incorporated into such electronic apparatuses has been configured so as to include a number of circuit elements. Integration density of such a semiconductor device (integrated circuit device) can be increased by using a three-dimensional stacked semiconductor device.
However, conventional techniques do not disclose wiring on the back surface of a three-dimensional stacked semiconductor device (hereinafter such wiring may be referred to as “back wiring”). Back wiring on a device enables the device to be freely connected (stacked) on another component in three dimensions, and thus the device exhibits drastically increased degree of freedom in terms of combination.
Through-electrodes have conventionally been formed through a complicated high-cost process, and thus demand has arisen for a low-cost technique for forming through-electrodes. Conventionally, surfaces (walls) defining through-holes have been insulated through formation of a thermally oxidized film or through a CVD process. However, such a process requires high-temperature treatment, and thus is difficult to apply to a semiconductor device mounting process. Such a mounting process, in which insulation of through-hole-defining surfaces is carried out after LSI wiring, requires a process for insulating through-hole-defining surfaces at the lowest possible temperature. That is, there is still room for improvement in methods for forming through-holes in a semiconductor substrate and for insulating the through-holes.
Patent Documents 1 and 2, which are known publications, disclose only a method for forming a thermally oxidized film at low temperature.
Patent Document 3 and 4 disclose a technique for forming through-electrodes in semiconductor bare chips, and stacking the chips in three dimensions. However, each of the patent documents discloses only a structure whose rigidity is secured by merely a silicon substrate. Therefore, the structure requires a silicon substrate having a predetermined thickness (e.g., 50 μm or more), and thus requires deep through-holes, leading to difficulty in forming through-electrodes.
Patent Document 1: Japanese Patent Application Laid-Open (kokai) No. 2003-086591
Patent Document 2: Japanese Patent Application Laid-Open (kokai) No. 2002-237468
Patent Document 3: Japanese Patent Application Laid-Open (kokai) No. 2003-309221
Patent Document 4: Japanese Patent Application Laid-Open (kokai) No. H10-223833